1. Field of the Invention
An embodiment of the present invention relates to the test field. More specifically, embodiments relate to the test of memory devices.
2. Discussion of the Related Art
The memory devices are generally subject to a test (for example, a functional test) to verify their correct operation; this is of the utmost importance to ensure a high quality of the production process of the memory devices. However, with the increase of the integration of memory devices, the difficulties of execution of the functional test accordingly increase, thereby making such functional test not always reliable and accurate.
A class of memory devices that has a very high integration, called VLSI (Very Large Scale of Integration), is represented, for example, by static random access memory devices, or SRAM (Static Random Access Memory). Typically, a generic memory device includes a matrix of memory cells, each one of which can store a binary information, or bit (i.e., the logic value “0” or “1”); the memory device also includes corresponding peripheral circuits, which in general accomplish functions of management and access to the memory cells.
The high integration to which such memory devices are subject makes it difficult to run their functional test according to standard methodologies, for example, through the use of probes for accessing input/output pins of the memory device. In fact, in this case it turns out to be not easy to make the probing with such pins precisely without damaging them; moreover, the probing of the pins in any case does not ensure a direct access to input/output terminals of the memory matrix and/or of the peripheral circuits. For this reason, the memory devices are also usually provided with a test apparatus, called BIST (Built-In Self Test) machine, which, by directly contacting the input/output terminals of the memory device, independently runs the functional test of the memory device. To such purpose, the BIST machine performs write operations of predefined bits on each memory cell, followed by read operations of the bits being just written; according to a comparison between the read bits and their expected values, the BIST machine outputs a result of the functional test. Such result is simply a flag indicating the success or the failure of the functional test and, if necessary, an indication of a number of errors (i.e., mismatches between read bits and expected values) that have occurred in the course of the functional test. In such way, the execution of the functional test requires the exchange of simple signals (for its activation and for outputting its result) to few pins of the memory device (for example, through a JTAG interface).
Although widely used, such functional test allows obtaining only general information about the state of the whole memory device; in fact, the write and read operations being performed by the BIST machine during the execution of the functional test involve different functional blocks, including the memory cells and the (write and read) peripheral circuits of the memory device. For this reason, in case of failure of the functional test of the memory device it is not possible to determine to which one of the functional blocks the failure is due.
In addition, within the peripheral circuits, the failure may be in different components—for example, write multiplexers or read multiplexers (used for transferring data to or from the memory cells being selected during the write or read operations, respectively), write drivers (used for writing the selected memory cells), sense amplifiers (used for reading the selected memory cells) or bit lines (used for coupling the memory cells with the multiplexers).
For this reason, if it is desired to perform a failure analysis for identifying a cause of the failure within a function block of the memory device (i.e., the memory cells or a component of the peripheral circuits) and for providing corresponding solutions, no indication would be available neither about the functional block to be examined, nor least of all about the component on which the attention has to be focused; therefore, such failure analysis would require very long times, being sometimes incompatible with the project timing being requested nowadays.
In its general terms, the solution according to one or more embodiments of the present invention proposes using auxiliary memory cells storing fixed values for checking the functionality of the memory device.
In particular, one or more aspects of the solution according to an embodiment of the invention are set out in the independent claims, with advantageous features of the same solution that are indicated in the dependent claims (whose wording is enclosed herein verbatim by reference).